Large scale integrated circuits or other integrated devices are designed through a complex sequence of transformations that convert an original performance specification into a specific circuit structure. Automated software tools are currently used for many of these design transformations. The description of the circuit at this stage is often called a “netlist”.
Automated tools exist to convert this netlist into a physical layout for the circuit. FIG. 1 illustrates one approach to conversion of the netlist to a physical layout. The layout defines the specific dimensions of the gates, isolation regions, interconnects, contacts, and other device elements that form the physical devices, and usually represents these shapes with polygons defining their boundaries.
The layout typically contains data layers that correspond to the actual layers to be fabricated in the circuit. The layout also contains cells, which define sets of particular devices within the circuit. Cells typically contain all the polygons on all the layers required for the fabrication of the devices it contains. Cells can be nested within other cells, often in very intricate arrangements. The structure of cells is often called a data hierarchy. Typical formats for the polygons of a physical layout are GDS II, CIF or OASIS.
Once the layout is created, the layout is verified to ensure that the transformation from netlist to layout has been properly executed and that the final layout created adheres to certain geometric design rules. These layout verification operations are often called LVS (layout versus schematic) and DRC (design rule check), respectively. To perform this verification step, several products have been created, including DRACULA™ from Cadence Design Systems of San Jose, Calif., HERCULES™ from Synopsis Corporation of Mountain View, Calif., and CALIBRE® from Mentor Graphics of Wilsonville, Oreg. When anomalies or errors are discovered by these checking tools, the designer must then repair the fault before the layout is sent to a mask shop for mask manufacturing and wafer fabrication.
An additional checking step can also be used for layout verification. FIG. 2 illustrates an enhanced approach to conversion of the netlist to a physical layout. This provides a simulation based software engine that predicts what manufacturing distortions will occur during lithographic patterning. If the magnitude of these errors is determined to be significant, corrections are made using some form of Optical and Process Correction (OPC). OPC can correct for image distortions, optical proximity effects, photoresist kinetic effects, etch loading distortions, and other various process effects. Phase-shifting features can also be added to the layout at this point to enhance contrast.
Examples of this kind of checking and correction can be found in “Automated Determination of CAD Layout Failures Through Focus: Experiment and Simulation,” by C. Spence et. al, in Optical/Laser Microlithography VII, Proc. SPIE 2197, p. 302 ff. (1994), and “OPTIMASK: An OPC Algorithm for Chrome and Phase-shift Mask Design” by E. Barouch et al. in Optical/Laser Microlithography VIII, Proc. SPIE 2440, p. 192 ff. (1995). The prior art techniques mentioned above comprise operating on the layout with a series of distinct software tools that execute all the required steps in sequence.
FIG. 3 is a conceptual illustration of an example of such a prior art process of integrated circuit (IC) design verification and correction. Each of the required process steps is executed by a stand-alone software tool. Original IC layout 300 describes the physical circuit layers from which masks and/or reticles are created to realize the circuit described by the design layout: the original IC layout 300 can be, for example, a GDS-II description of the circuit to be manufactured.
Data import process 310 converts original IC layout 300 to a format for storage in database 315. The data, as stored in verification database 315, is used by layout versus schematic (LVS) tool 320 and design rule checking (DRC) tool 325 to verify the design of original IC layout 300. Upon completion of LVS and DRC verification, the data stored in verification database 315 is exported by data export process 330.
The data is then imported by a data import process 335, which converts the exported data to a format used for a phase shift mask (PSM) database 340. PSM tool 345 operates on the data stored in PSM database 340 to perform phase shifting where appropriate. Examples of stand alone PSM assignment tools are SEED, discussed in the reference by Barouch, above, and the IN-Phase™ product available from Numerical Technologies of San Jose, Calif. The data describing the phase shifted layout(s) are exported from PSM database 340 by a data export process 350.
A data import process 355 imports the data generated by the PSM tool to an optical process correction (OPC) database 360. OPC database 360 is typically a flat database, meaning that all the polygons of a layer of the circuit are contained within a single cell, with no hierarchical structure. Data import process 355 typically converts data from a hierarchical representation to a flat representation. OPC tool 365 performs OPC operations on the data stored in OPC database 360. Examples of stand alone OPC tools are OPTIMASK, discussed in the reference by Barouch, above, and Proteus™ available from Synopsis Corporation. A data export process 370 exports the data stored in OPC database 360.
The data generated by the OPC tool is then typically imported into a simulation tool, to confirm that the OPC will have the desired corrective effect. This is sometimes called an optical and process rule check, or ORC. ORC checks can be run before OPC to determine if OPC is even necessary, at an intermediate point in an OPC run to determine if the results are good enough or after OPC has been completed. Once this check is complete, the data is exported for use in IC manufacturing process 395. As a final verification step, LVS tool 320 and/or DRC tool 325 can also be used on the output of OPC database 360. Performing another check with LVS tool 320 and/or DRC tool 325 requires another import and export by data import process 310 and data export process 330, respectively.
Several problems exist with respect to the process illustrated in FIG. 3. For example, the importation and exportation of data to and from each tool provides an opportunity for error in the form of loss, or inaccurate translation, of data. The importation and the exportation of large datasets, now common for VLSI ICs, is also time consuming, where a single import or export step can last several hours. The more complex an integrated circuit design, the more time consuming the importation and exportation steps become. It is therefore desirable to have a new verification tool in which all the required operations can be preformed, but where the risk of inaccurate translation is eliminated, and the many time consuming import and export steps are not required.